Mycket duktig inom SOC med många väl genomförda uppdrag. Har kapacitet att vara teamlead eller projektledare. SHORT PROFILE BSc in Electronics Engineering and have over 15 years of VHDL based Top-Down complex ASIC/FPGA and SOC design experience and experience of synthesis (Synopsys tool & COMPASS tools & others), and backend flow, including backannotation, P & R and clock tree generation and static timing analyses. Knowledge and experience of microprocessor based design, Bluetooth baseband, C/C++, Assembler, SystemVerilog, UVM, experience with Xilinx webpack (ISE) and Vivado, Synopsys, Mentor, Cadence, Cadence Xcelium, Synplicity, Intel Quartus, AHB Bus and has effective communication skills, flexibility and strong teamwork approach.

Log in to make an inquery for this profile
Username
Password